Intel vs TSMC: Diverging Paths in High-NA Lithography 2026

Daniel Harrolds
Intel vs TSMC: Diverging Paths in High-NA Lithography
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Intel and TSMC have taken radically different paths with High-NA lithography, the next-generation chipmaking technology from ASML. Intel has already processed over one million wafers using its High-NA extreme ultraviolet (EUV) machines, while TSMC remains more cautious. This divergence could reshape the competitive landscape in semiconductor manufacturing.

High-NA lithography enables finer patterns on silicon wafers than conventional EUV, but it comes with a significant trade-off: producing large chips is more difficult. The anamorphic optics in High-NA machines reduce the exposure field to 26 x 16.5 mm, down from 26 x 33 mm with standard EUV. This means chipmakers must use two exposures to pattern large dies, a technique known as stitching.


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Intel's High-NA Milestone: One Million Wafers

Intel's announcement that it has processed over one million wafers with High-NA EUV machines is impressive, but the figure includes wafers used during installation, certification, R&D, and production. It does not mean one million wafers were fully produced using High-NA lithography. Nevertheless, the milestone underscores Intel's commitment to the technology.

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The company has been working with High-NA machines for over two and a half years. Under the leadership of Lip-Bu Tan, Intel has positioned itself as an early adopter, aiming to regain process leadership. By integrating High-NA into its manufacturing flow, Intel hopes to achieve better resolution and smaller features, which are critical for advanced nodes.

TSMC's Cautious Approach to High-NA

In contrast, TSMC has taken a more conservative stance. The Taiwanese giant has expressed concerns about the cost and complexity of High-NA lithography, particularly the stitching requirement for large chips. TSMC plans to continue using conventional EUV for its upcoming nodes, only adopting High-NA when it becomes economically viable.

This strategy reflects TSMC's focus on yield and cost-effectiveness. As the world's largest chipmaker, TSMC cannot afford to disrupt its high-volume manufacturing. By waiting, it can learn from early adopters and avoid potential pitfalls.

Why the Divergence Matters

The different approaches highlight a fundamental strategic choice. Intel, which has lost ground to TSMC in recent years, is betting on High-NA to leapfrog the competition. TSMC, on the other hand, is leveraging its manufacturing prowess and customer relationships to maintain its lead.

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If High-NA delivers on its promise, Intel could gain a significant advantage in producing the most advanced chips. But if the technology proves too costly or complex, TSMC's patience could pay off. The outcome will influence not only the two companies but also the entire semiconductor supply chain. The background to this story is set out in TSMC's New Chip Campus: Why Neither Option Is in Europe. A related thread runs through Rapidus Aims to Lure TSMC Customers to Japan's Chip Industry.

Key Takeaways

  • Intel has processed over one million wafers with High-NA EUV machines, including installation and R&D.
  • High-NA lithography offers finer resolution but requires stitching for large chips, increasing complexity.
  • TSMC is delaying High-NA adoption, focusing on cost and yield with conventional EUV.
  • The divergence reflects Intel's push for leadership and TSMC's defensive strategy.
  • The industry watches to see which approach yields better results.

High-NA vs Conventional EUV: Key Differences

Feature High-NA EUV Conventional EUV
Exposure field 26 x 16.5 mm 26 x 33 mm
Resolution Higher Standard
Large chip production Requires stitching Single exposure
Adoption status Early (Intel) Mature (TSMC, Samsung)

What to Watch Next

Investors and industry observers should monitor Intel's progress in ramping High-NA production. Any delays or yield issues could validate TSMC's caution. Meanwhile, TSMC's roadmap for High-NA adoption will signal when the technology becomes mainstream. Earlier coverage in Sinfields Take Diverging Paths on Road to Super League Grand Final shows how the argument developed. A closer look at the same subject appears in TSMC Commits 250 Billion to US Semiconductor and AI Production.

The competition between Intel and TSMC is not just about technology; it's about business models and risk management. Intel's bold move contrasts with TSMC's calculated patience. As the semiconductor industry evolves, the lessons from this divergence will shape future strategies. Anyone following the wider picture can start with Business: latest articles. The same theme surfaces in Nanya Technology's $16B DRAM Bet to Ease Memory Chip Crisis, which takes a different angle.

FAQ

What is High-NA lithography?

What is High-NA lithography?

High-NA lithography is an advanced chipmaking technology that uses high-numerical-aperture optics to print finer patterns on silicon wafers. It is the successor to conventional EUV lithography and is expected to enable more powerful chips.

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Why does High-NA require stitching for large chips?

The anamorphic optics in High-NA machines reduce the exposure field to 26 x 16.5 mm, half the size of conventional EUV. To pattern larger chips, two exposures must be stitched together, increasing complexity and cost.

Is TSMC using High-NA lithography?

TSMC has not yet adopted High-NA for mass production. The company is evaluating the technology but plans to continue using conventional EUV for its near-term nodes, citing cost and yield considerations.

What does Intel's one million wafer milestone mean?

Intel's milestone includes wafers processed during installation, certification, R&D, and production. It indicates significant experience with High-NA tools but does not mean one million wafers were fully produced using the technology.

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Daniel Harrolds

Author

Daniel Harrolds

With a career spanning four decades, Daniel is almost a library in the field of precious metals investing and Gold IRAs. His insightful strategies and pragmatic results-oriented approach make him a resource in safeguarding wealth, and financial foresight.


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